Title :
Mixed sensing architecture for 64 Mbit 16-level-cell nonvolatile memories
Author :
Calligaro, C. ; Manstretta, A. ; Rolandi, P. ; Torelli, G.
Author_Institution :
Dipartimento di Elettronica, Pavia Univ., Italy
Abstract :
This paper presents a sensing architecture for multilevel non-volatile memories. Sensing is carried out following a dichotomic algorithm, where each search step performs a number of parallel comparisons. Two sensing steps are able to detect as many as 16 levels (4 bits) when using three sense amplifiers per cell to be detected. The architecture is suitable for 16 Mcells (64 Mbit) EPROMs, where the memory cells are factory programmed to guarantee the tight threshold voltage distribution required for reliable store and sense
Keywords :
EPROM; cellular arrays; memory architecture; multivalued logic; 64 Mbit; EPROMs; dichotomic algorithm; mixed sensing architecture; multilevel memories; nonvolatile memories; parallel comparisons; sense amplifiers; sensing architecture; threshold voltage distribution; Circuits; Consumer electronics; EPROM; Electronic mail; Fabrication; Nonvolatile memory; Production facilities; Read only memory; Silicon; Threshold voltage;
Conference_Titel :
Innovative Systems in Silicon, 1996. Proceedings., Eighth Annual IEEE International Conference on
Conference_Location :
Austin, TX
Print_ISBN :
0-7803-3639-9
DOI :
10.1109/ICISS.1996.552420
