A fast round robin priority port scheduler for high capacity ATM switches

This paper presents a novel architecture and implementation of a round-robin scheduler (RRS) for high capacity ATM switches. The objective is to select a port from a set of alternating real-time/non real-time priority ports, based on the priority of the port, the minimum cell-rate (MCR) assigned to the ports and the backpressure signals coming from the output buffers. Using a novel scheme, the characteristics of the scheduler were transformed into a finite state machine description, and a fast implementation of it was derived using a binary tree. The nodes in the binary tree act as “cut through” switches, and thus the scheduler is able to operate at high speed. This solution is amenable for implementation in high speed silicon technology. It is compact in terms of logic gate requirements and is very scalable. We believe that this RRS is a viable option in gigabit ATM switches