Hardware Implementation of ADABOOST ALGORITHM and Verification

Adaboost algorithm is difficult to implement on embedded platform for real-time face detection by software due to its high computation load and data throughput. This article presents a cell array architecture using parallel technology. Detection procedure can be greatly speeded up with its multi- pipeline. Besides it makes use of the continuity of image data to decrease the accesses to RAM. This article uses Electronic System Level (ESL) tools to develop and simulate a cycle-accurate model of the cell array architecture. The result shows that cell array architecture with 200 MHz clock can process 12 million HAAR features per second and detect faces on a 176*144 image at the frame rate of 103 frames per second, which is 14 times speedup compared with software implementation.