Scalable hardware and software architecture for radar signal processing system

The conventional approach to digital signal processing in radar systems involves hardware realization with the use of specialized integrated circuits. Such an approach is lacking in versatility and scalability. Advances in digital signal processor (DSP) technology make it possible to realize nearly all algorithms in software, using general-purpose DSP chips (cf. Edwards and Wilkinson 1996). Such an approach has many advantages as it can be easily adapted to changing (growing) users demand. In the current paper the latter method is considered in detail and a scalable architecture of hardware and software adequate for radar signal processing is derived. Typical radar systems require a total workload of the order of 1-10 Gflops. Comparing this figure with the 50 Mflops average performance of a modern floating-point DSP evidently one has to use about 100 processors in a single system. Therefore, both the topology of their connections and methods of paralleling processing algorithms are very important