Improving Run Times by Pruned Application of Synthesis Transforms

Author

Hentschke, Renato F. ; Narasimhan, Jagannathan ; Kung, David

Author_Institution

IBM Research, 1101 Kitchawan Rd. Yorktown Heights, NY 10598; Universidade Federal do Rio Grande do Sul - Av. Bento Gonqalves, 9500. Bloco IV. CP 15064 CEP 91501-970 Porto Alegre Brazil. +55-51 84079005, renato@inf.ufrgs.br

fYear

2005

fDate

4-7 Sept. 2005

Firstpage

38

Lastpage

43

Abstract

In this paper, we describe methods to speed up integrated placement and synthesis of high performance designs. We present an analysis of the computation times of various logic synthesis transforms. We then show techniques to reduce computation time based upon judicious selection of gates and nets for the resizing and buffering transforms, respectively. We show that it is possible to obtain savings of up to 28% in CPU time without compromising the quality of the results. For large high performance designs that are quite common these days our savings could translate into several hours of CPU time.

Keywords

Algorithm design and analysis; Central Processing Unit; Design automation; Design optimization; Driver circuits; Filtering algorithms; Integrated circuit synthesis; Logic; Permission; Timing; Algorithms; Buffering; Driver; Experimentation; Filtering; Performance; Resizing; Synthesis;

fLanguage

English

Publisher

ieee

Conference_Titel

Integrated Circuits and Systems Design, 18th Symposium on

Print_ISBN

1-59593-174-0

Type

conf

DOI

10.1109/SBCCI.2005.4286829

Filename

4286829