• DocumentCode
    3219057
  • Title

    Miriã_SI: A Tool for the Synthesis of Speed-Independent Multi Burst-Mode Controllers

  • Author

    De Oliveira, Duarte Lopes ; Strum, Marius ; Chau, Wang Jiang

  • Author_Institution
    Inst. Tecnologico de Aeronautica, Sao Paulo
  • fYear
    2005
  • fDate
    4-7 Sept. 2005
  • Firstpage
    56
  • Lastpage
    61
  • Abstract
    Asynchronous controllers are very efficient to operate as high performance interfaces in heterogeneous synchronous/asynchronous systems. Asynchronous controllers may be designed to operate either in the generalized fundamental mode (GFM) or in the input-output (I/O) mode. The latter are more robust to temperature variation and technology migration and may operate in faster environments. However, none of the existing synthesis tools, targeting circuits that operate in the I/O mode accept non-monotonic level sensitive signals (usually adopted to describe conditions in heterogeneous systems). Another limitation of these synthesis tools concerns the number of signals that may be present in the initial specification. This limitation comes from the input description that must be either a signal transition graph (STG) or a state graph (SG). In this article we present Miria-SI, an extension of the Miria-GFM synthesis tool that can synthesize such circuits. It starts from a state transition description known as multi-burst graph that is able to accept up to 200 signals. Nonmonotonic signals are nicely handled. The resulting controllers, implemented in the feedback set-dominant latch architecture are guaranteed to be hazard free
  • Keywords
    asynchronous circuits; controllers; high level synthesis; logic CAD; Miria-GFM; Miria_SI; asynchronous controller; asynchronous logic; automatic synthesis; circuit synthesis tool; generalized fundamental operation; heterogeneous synchronous-asynchronous system; input-output operation; latch architecture; logic design; multi burst-mode controller synthesis; multiburst graph; nonmonotonic signal handling; signal transition graph; state graph; state transition description; system interface; Algorithm design and analysis; Circuit synthesis; Communication system control; Control system synthesis; Control systems; Delay; Hazards; Latches; Logic design; Signal synthesis; Algorithms; Design; Performance; asynchronous logic; automatic synthesis; burst-mode; hazard; speed-independent;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Integrated Circuits and Systems Design, 18th Symposium on
  • Conference_Location
    Florianopolis
  • Print_ISBN
    1-59593-174-0
  • Type

    conf

  • DOI
    10.1109/SBCCI.2005.4286832
  • Filename
    4286832