Compact and simple output transition time model in nanometer CMOS gates

Author

Alioto, Massimo ; Poli, Massimo ; Palumbo, Gaetano

Author_Institution

Dipt. di Ing. dell´´Inf. (DII), Univ. di Siena, Siena, Italy

fYear

2008

fDate

14-17 Dec. 2008

Firstpage

264

Lastpage

267

Abstract

This paper presents a model of the output transition time suitable for nanometer CMOS gates. The proposed modeling approach separately analyzes the output transition time under fast and slow inputs, according to the basic concept of the model in. The model so developed is very simple and preserves a clear physical meaning. These highly desirable characteristics allow for an efficient implementation in CAD tools, as well as an easy scalability between different processes. Spectre simulations on a 45 nm Berkeley Predictive Technology Model (BPTM) show that the model accuracy is about 4%.

Keywords

CMOS integrated circuits; circuit CAD; circuit simulation; nanoelectronics; Berkeley Predictive Technology Model; CAD tools; nanometer CMOS gates; output transition time; scalability; size 45 nm; spectre simulations; CMOS technology; Circuits; Computational efficiency; Delay estimation; Predictive models; Scalability; Semiconductor device modeling; Telephony; Timing; Very large scale integration; CMOS; Timing model; VLSI; timing analysis; transition time;

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronics, 2008. ICM 2008. International Conference on

Conference_Location

Sharjah

Print_ISBN

978-1-4244-2369-9

Electronic_ISBN

978-1-4244-2370-5

Type

conf

DOI

10.1109/ICM.2008.5393823

Filename

5393823