Placement of Intermodule Connections on Partially Reconfigurable Devices

This paper presents algorithms for the placement of intermodule signals on dynamically and partially reconfigurable devices. Intermodule signals facilitate communication across reconfigurable module boundaries on FPGA devices and must guarantee conformance to partial reconfiguration requirements, i.e., they must represent static and fixed communication resources. Beside the realization of such communication as reliable signals, the physical location must be conform to all possible abutting modules, particularly if different modules with different communication requirements are temporally loaded into the same physical location. In this paper, we investigate the requirements for the placement of signals for such temporal changing conditions. After presenting and categorizing critical scenarios, we formalize strategies to find valid locations for the intermodule signals. Considering the dynamically loadable modules and their connections as a graph, we can avoid signal conflicts, if the physical allocation of the signals harmonizes with all modules in the nearest and second nearest neighboring range. In order to prove the applicability, we test our developed algorithms for different scenarios