Title :
Modeling and characterization of HDTMOS power technology
Author :
Hossain, Zia ; Venkatraman, Prasad ; Sundaram, Sam
Author_Institution :
On Semicond., Phoenix, AZ, USA
Abstract :
The HDTMOS (third generation high density TMOS) technology for low voltage power MOSFETs utilizes a self aligned sidewall spacer to reduce the source contact window. The five layer cell design yields one of the best performing power MOSFETs in the industry for switching applications. 2D process and device simulation of the ISE software package has been used extensively to optimize the device design for the best performance. The actual silicon data is compared to simulation for the validation of modeling work. Further improvements to enhance the performance of HDTMOS3, called HDTMOS3E are discussed
Keywords :
optimisation; power MOSFET; power semiconductor switches; semiconductor device models; technology CAD (electronics); 2D process simulation; HDTMOS power technology; HDTMOS3 performance; HDTMOS3E performance; ISE software package; device design optimization; device simulation; five layer cell design; low voltage power MOSFET; model validation; modeling; power MOSFETs; self aligned sidewall spacer; silicon data; simulation; source contact window; switching applications; third generation high density TMOS technology; Electric breakdown; FETs; Fabrication; Immune system; Implants; Metallization; Organizing; Silicon; Substrates; Systems engineering and theory;
Conference_Titel :
Semiconductor Electronics, 2000. Proceedings. ICSE 2000. IEEE International Conference on
Conference_Location :
Guoman Port Dickson Resort
Print_ISBN :
0-7803-6430-9
DOI :
10.1109/SMELEC.2000.932308
