Efficient methodology for boundary scan insertion and pattern generation for MCM based designs

The standard IEEE 1149.1 poses a challenge when used for MultiChipModule designs. In this paper, a novel and efficient method to insert and test boundary scan circuitry in a MultiChipModule design has been proposed. Our strategy imposes minimal additional hardware during boundary scan insertion, and minimal manual intervention during the boundary scan pattern generation, while complying with the IEEE 1149.1 standard. The proposed method is implemented on a sample MultiChipModule design which consists of all kinds of pins and interconnects between the cores. Experimental results are presented to prove the presented scheme.