On the adders with minimum tests

Author

Kajihara, Seiji ; Sasao, Tsutomu

Author_Institution

Dept. of Comput. Sci. & Electron., Kyushu Inst. of Technol., Fukuoka, Japan

fYear

1997

fDate

17-19 Nov 1997

Firstpage

10

Lastpage

15

Abstract

This paper considers two types of n-bit adders, ripple carry adders and cascaded carry look-ahead adders, with minimum tests for stuck-at-fault models. In the first part, we present two types of full adders consisting of five gates, and show their minimality. We also prove that one of the full adders can be tested by only three test patterns for single stuck-at-faults. We also present two types of 4-bit carry look-ahead adders and their minimum rests. In the second part, we consider the tests for the cascaded adders, an n-bit ripple carry adder and a 4m-bit cascaded carry look-ahead adders. These tests are considerably smaller than previously published ones

Keywords

adders; cascade networks; fault location; logic design; logic testing; 4m-bit cascaded carry look-ahead adders; cascaded carry look-ahead adders; minimum tests; n-bit adders; n-bit ripple carry adder; ripple carry adders; single stuck-at-faults; stuck-at-fault models; Adders; Arithmetic; Circuit faults; Circuit testing; Combinational circuits; Computer science; Electronic equipment testing; Fault detection; Logic arrays;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Symposium, 1997. (ATS '97) Proceedings., Sixth Asian

Conference_Location

Akita

ISSN

1081-7735

Print_ISBN

0-8186-8209-4

Type

conf

DOI

10.1109/ATS.1997.643907

Filename

643907