Test generation for stuck-on faults in BDD-based pass-transistor logic SPL

Author

Shinogi, Tsuyoshi ; Hayashi, Terumine ; Taki, Kazuo

Author_Institution

Fac. of Eng., Mie Univ., Tsu, Japan

fYear

1997

fDate

17-19 Nov 1997

Firstpage

16

Lastpage

21

Abstract

This paper presents a method of test generation for stuck-on faults in a pass-transistor logic SPL by logic testing. We describe how to create a discrepancy using a pre-computed table for voltage calculation. For solving a table explosion problem we present some techniques for extending the applicable scope of a restricted table in practical size. Then, we propose a simple DFT circuit. The experimental results show the effectiveness

Keywords

CMOS logic circuits; combinational circuits; decision tables; design for testability; logic design; logic testing; BDD; DFT circuit; binary decision diagrams; effectiveness; fault activation; logic testing; pass-transistor logic SPL; pre-computed table; restricted table; single-rail pass-transistor logic; stuck-on faults; table explosion; test generation; voltage calculation; Binary decision diagrams; Boolean functions; CMOS logic circuits; Circuit faults; Circuit simulation; Circuit testing; Data structures; Large scale integration; Logic testing; MOSFETs;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Symposium, 1997. (ATS '97) Proceedings., Sixth Asian

Conference_Location

Akita

ISSN

1081-7735

Print_ISBN

0-8186-8209-4

Type

conf

DOI

10.1109/ATS.1997.643908

Filename

643908