DocumentCode
3220401
Title
Testability features of R10000 microprocessor
Author
Mori, Junji ; Mathew, Ben ; Burns, Dave ; Mok, Yeuk-Hai
Author_Institution
Toshiba Corp., Kawasaki, Japan
fYear
1997
fDate
17-19 Nov 1997
Firstpage
108
Lastpage
111
Abstract
This paper describes the testability design features of the R10000 microprocessor. It has specific testability features for debug and manufacturing purposes. Observability registers are implemented to enhance high fault coverage and they partition the chip into three parts to run a fault simulation much faster. Plus a clock control mechanism for AC path analysis and a minimal impact embedded memory test feature are implemented
Keywords
computer testing; design for testability; digital simulation; integrated circuit testing; logic design; observability; AC path analysis; R10000 microprocessor; clock control; debug; fault simulation; manufacturing; minimal impact embedded memory test; observability registers; testability features; Automatic test pattern generation; Automatic testing; CMOS technology; Clocks; Controllability; Logic testing; Manufacturing; Microprocessors; Observability; Registers;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Symposium, 1997. (ATS '97) Proceedings., Sixth Asian
Conference_Location
Akita
ISSN
1081-7735
Print_ISBN
0-8186-8209-4
Type
conf
DOI
10.1109/ATS.1997.643930
Filename
643930
Link To Document