Title :
Biased two´s complement representation for low-power DSP systems
Author :
Khoo, Kei-Yong ; Chen, Chao-Liang ; Willson, Alan N., Jr.
Author_Institution :
Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA
Abstract :
This paper shows that the switching activity of the sign-extended bits in a two´s complement number in a DSP system can be reduced by the application of a bias to the system´s input. The technique is easy to implement and requires only one to two additional adders. Experimental results show a 20% and 5% reduction in bit-switching activities for a typical voice grade signal and an FIR filter processing the signal, respectively
Keywords :
CMOS digital integrated circuits; FIR filters; adders; digital arithmetic; digital signal processing chips; FIR filter; adders; biased two´s complement representation; bit-switching activities; low-power DSP systems; sign-extended bits; switching activity; voice grade signal; Arithmetic; Capacitance; Convolution; Data communication; Digital signal processing; Dynamic range; Finite impulse response filter; Frequency response;
Conference_Titel :
Circuits and Systems, 1997. Proceedings of the 40th Midwest Symposium on
Conference_Location :
Sacramento, CA
Print_ISBN :
0-7803-3694-1
DOI :
10.1109/MWSCAS.1997.662192
