DocumentCode
3220528
Title
Wireless Sensor Nodes Processor Architecture and Design
Author
El Kateeb, Ali ; Ramesh, Aiyappa ; Azzawi, L.
Author_Institution
Univ. of Michigan, Dearborn
fYear
2008
fDate
25-28 March 2008
Firstpage
892
Lastpage
897
Abstract
In this paper, a specialized soft processing core for sensor nodes has been designed and implemented. The paper presents a detailed view of architecture and the instructions set of the processor. The core can be easily integrated with other sensor node parts to construct different types of nodes that can be used to support different sensor network applications. The core is implemented using Xilinx ISE 8.2i design tools. The architecture of the core is simple and can process 10.78 MIPS.
Keywords
microprocessor chips; wireless sensor networks; Xilinx ISE 8.2i; processor architecture; wireless sensor nodes; Arithmetic; Clocks; Computer architecture; Counting circuits; Microprocessors; Process design; Registers; Security; Sensor phenomena and characterization; Wireless sensor networks; FPGA; Processor; sensor nodes;
fLanguage
English
Publisher
ieee
Conference_Titel
Advanced Information Networking and Applications - Workshops, 2008. AINAW 2008. 22nd International Conference on
Conference_Location
Okinawa
Print_ISBN
978-0-7695-3096-3
Type
conf
DOI
10.1109/WAINA.2008.177
Filename
4483029
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