Low-Power High-Performance and Dynamically Configured Multi-Port Cache Memory Architecture

As on-chip cache size has increased considerably in recent high-performance microprocessor technologies, power dissipation and leakage current in SRAM have become critical. High-performance IC designs use multi-port cache memory to provide the needed accessibility and bandwidth. Since the word and bit lines cover the foot-print of the entire cache section, duplicating the word and bit lines for multiple ports results in large silicon area and increases bitline discharge and power dissipation. As technology scales down device size and supply voltages, static power dissipation has emerged as a critical factor in total system power dissipation. In this paper, we present an area-and energy-efficient multi-port cache memory architecture, which employs isolation nodes, local sense amplifiers and dynamic memory partitioning techniques, to facilitate simultaneous multi-port accesses without duplicating bitlines. The proposed cache memory architecture also reduces bitline latency.