VLSI implementation of synchronizer and pipelined CORDIC in OFDM receiver for fourth generation wireless LAN applications

This paper deals with VLSI implementation of synchronizer and pipelined CORDIC algorithm for OFDM based applications. The function of synchronizer is autocorrelation. The autocorrelator is used for frame detection and carrier frequency offset estimation in fourth generation wireless communication applications. The CORDIC is effectively used at OFDM receiver to estimate the frequency offset and to calculate the division algorithm for channel estimation. A fast pipelined CORDIC architecture and autocorrelator is designed, implemented and tested by using 130nm technology. Matlab simulations are performed prior to the Verilog HDL coding for functional verification. The design parameters of autocorrelator and fast pipelined CORDIC on three different Xilinx FPGA target devices are noted. Finally the area, power and delay reports are observed.