Factors Limiting the Device Performance in Power FLIMOSFET: 2-D Simulation Study

In this paper, we present numerical simulation results for a power FLIMOSFET structure. Extensive simulations were performed to understand the device physics through various internal electrical quantities like potential distribution, electric field, etc in different regions of the device both in on/off states. It has been shown that although the floating islands concept tend to decrease the peak electric field in the drift region, there are some degrading factors effecting the device performance such as breakdown voltage tend to decrease with the increase in the number of floating islands and the I-V characteristics show a current limiting phenomenon at high gate and drain voltages known as quasi-saturation due to velocity saturation.