DocumentCode
3221147
Title
On the capability of delay tests to detect bridges and opens
Author
Chakravarty, Sumit
Author_Institution
Intel Corp., Santa Clara, CA
fYear
1997
fDate
17-19 Nov 1997
Firstpage
314
Lastpage
319
Abstract
Recent empirical and simulation studies show that adding at-speed testing to the test suite helps in detecting defective ICs missed by slow-speed and IDDQ testing. At-speed testing attempts to detect ICs with defects, like bridges and opens, which cause faulty dynamic logic behavior. Path delay tests and transition tests are two popular tests used during at-speed testing. We show that these tests often fail to detect many bridges and opens which cause faulty dynamic behavior. Computing at speed tests is therefore fundamentally different from computing delay tests for parametric testing and new techniques need to be developed
Keywords
automatic testing; delays; electric current measurement; fault location; integrated circuit testing; integrated logic circuits; logic testing; short-circuit currents; at-speed testing; bridges; defective IC; delay tests; faulty dynamic logic behavior; opens; path delay tests; simulation; transition tests; Bridge circuits; Circuit faults; Circuit testing; Computational modeling; Computer aided manufacturing; Computer science; Delay; Electrical fault detection; Fault detection; Logic testing;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Symposium, 1997. (ATS '97) Proceedings., Sixth Asian
Conference_Location
Akita
ISSN
1081-7735
Print_ISBN
0-8186-8209-4
Type
conf
DOI
10.1109/ATS.1997.643976
Filename
643976
Link To Document