DocumentCode
3221389
Title
Scaling rules allow the reuse of MOS analog design
Author
Galup-Montoro, C. ; Schneider, M.C. ; Coitinho, R.M.
Author_Institution
Dept. of Electr. Eng., Univ. Federal de Santa Catarina, Florianopolis, Brazil
fYear
2001
fDate
17-18 June 2001
Firstpage
8
Lastpage
9
Abstract
This paper presents a reuse procedure of analog circuits which is based on a scalable model of the MOSFET. A set of very simple expressions allows the calculation of the transistor dimensions and bias of a given circuit in a new generation technology, based on a previous design of the same circuit in an earlier technology.
Keywords
MOS analogue integrated circuits; electronic engineering education; integrated circuit design; integrated circuit modelling; MOS analog design; new generation IC technology; reuse procedure; scalable model; transistor dimensions; Analog circuits; Capacitance; Circuit simulation; Frequency; Integrated circuit technology; Libraries; MOSFET circuits; Signal to noise ratio; Temperature; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Microelectronic Systems Education, 2001. Proceedings. 2001 International Conference on
Print_ISBN
0-7695-1156-2
Type
conf
DOI
10.1109/MSE.2001.932393
Filename
932393
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