A high speed 12-bit pipelined ADC using Switched Capacitor and fat tree encoder

The parameters like speed and resolution of an analog to digital converter (ADC) characterizes the performance of any control system in the real world. Among available ADC architectures flash, pipeline, sigma-delta and successive approximation register (SAR) have been frequently used to satisfy different requirements like speed, resolution and power. A flash architecture is conceptually the simplest and the easiest to design, but requires a large number of transistors and significant power because, an n-bit ADC requires 2n-1 comparators (one comparator for each threshold), which also present a significant capacitive load to the circuitry driving the ADC. Though flash ADC is preferred for its high speed, this speed decreases with increase in resolution. In order to achieve higher resolution, SAR ADC is preferred, but the speed of the ADC is very limited. Therefore for better trade-off between resolution and speed, the pipeline architecture is used. The concurrent operation of the pipelined stages is responsible for its increased efficiency. Each stage processes a new sample as soon as its residue is sampled by the following stage, which leads to a high throughput of one sample per clock cycle. The pipeline ADC is constructed by using switched capacitor (SC) circuit, which exploits the charge storing abilities of CMOS to achieve precision signal processing and is preferred in mixed-signal, A/D interfaces. A fat tree encoder (FTE) used in Flash ADC of each pipeline stage improves speed, reduces the latency, power consumption and area.