Experiences in developing a research-focused project course: IP-core based IC design enabled by 3D wafer bonding

Author

Lü, Jian-Qiang ; Gutmann, Ronald J.

Author_Institution

Center for Integrated Electron. & Electron. Manuf., Rensselaer Polytech. Inst., Troy, NY, USA

fYear

2001

fDate

17-18 June 2001

Firstpage

89

Lastpage

90

Abstract

Three-dimensional (3D) integrations offer the potential of reducing fabrication and performance limitations of future generations of planar ICs. Our approach using dielectrics as the bonding glue layer provides a monolithic 3D integration process, which is fully compatible with back-end-of-the-line processing. This 3D technology enables heterogeneous systems, such as future electronic and photonic systems using a mix-and-match hard IP core design approach. We offer a new course on core-based IC design and technology, with both 2D and 3D implementations.

Keywords

VLSI; educational courses; electronic engineering education; industrial property; integrated circuit design; wafer bonding; 3D wafer bonding; IP-core based IC design; back-end-of-the-line processing; bonding glue layer; educational courses; heterogeneous systems; mix-and-match hard IP core design; planar ICs; research-focused project course; Application specific integrated circuits; Design methodology; Dielectric substrates; Fabrication; Integrated circuit interconnections; Manufacturing; Packaging; Photonic integrated circuits; System-on-a-chip; Wafer bonding;

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronic Systems Education, 2001. Proceedings. 2001 International Conference on

Print_ISBN

0-7695-1156-2

Type

conf

DOI

10.1109/MSE.2001.932428

Filename

932428