DocumentCode
3222499
Title
Multiple-valued product-of-sums expression with truncated sum
Author
Hata, Yutaka ; Kamiura, Naotake ; Yamato, Kazuharu
Author_Institution
Dept. of Comput. Eng., Himeji Inst. of Technol., Himeji, Japan
fYear
1997
fDate
28-30 May 1997
Firstpage
103
Lastpage
107
Abstract
Truncated sum (TSUM for short) can be useful for MV-PLAs realization. This paper introduces multiple-valued product-of-sums expressions where sum refers to TSUM and product does MIN. We investigate the multiple-valued product-of-sums expressions and show the minimization method and the simulation results. We describe the minimization method based on binary Quine-McCluskey algorithm. It is proved that in the minimal product-of-sums expressions, the implicate number of the expressions with TSUM is equivalent to the number of those with MAX. Next, we propose multiple-valued product-of-sums expressions with variables. The expressions involve the TSUM of variables and nonzero constants as the coefficients of the implicates. The minimization method is also proposed. Finally, we show the simulation results for some multiple-valued arithmetic functions. In them, an efficiency of the product-of-sums expressions with variables is shown and some comparisons are made
Keywords
logic design; minimisation of switching nets; multivalued logic; programmable logic arrays; MV-PLAs; TSUM; binary Quine-McCluskey algorithm; implicate number; minimization method; multiple-valued arithmetic functions; multiple-valued product-of-sums expression; nonzero constants; simulation results; truncated sum; Arithmetic; Charge coupled devices; Circuit simulation; Circuit synthesis; Field programmable gate arrays; Logic design; Logic functions; Minimization methods;
fLanguage
English
Publisher
ieee
Conference_Titel
Multiple-Valued Logic, 1997. Proceedings., 1997 27th International Symposium on
Conference_Location
Antigonish, NS
Print_ISBN
0-8186-7910-7
Type
conf
DOI
10.1109/ISMVL.1997.601381
Filename
601381
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