DocumentCode :
3223029
Title :
The EC Technology Challenges of Copper Deposition in Through Mask Application
Author :
Thieme, Tom
Author_Institution :
Atotech Deutschland GmbH, Berlin
Volume :
2
fYear :
2006
fDate :
5-7 Sept. 2006
Firstpage :
1133
Lastpage :
1136
Abstract :
The integration of electrochemically deposited copper into the wafer level packaging area has become an important and widely discussed topic. Besides the electrical and thermal advantages of copper interconnections, the dimensional stability is as well a beneficial feature for all new packaging designs and technologies. All corresponding industry applications, as there are copper pillar, redistribution layer, copper interconnections or deep silicon via filling are related to the balance of base chemical and additive ratio, as well as the process impact of the hydro dynamic flow conditions in different plating tool configurations
Keywords :
copper; electrodeposition; electronics packaging; interconnections; masks; silicon; Cu; EC technology; Si; additive ratio; base chemical; copper deposition; copper interconnections; copper pillar; deep silicon via filling; dimensional stability; electrochemical deposition; hydrodynamic flow conditions; plating tool configurations; redistribution layer; through mask application; wafer level packaging; Chemical industry; Chemical processes; Chemical technology; Copper; Filling; Industry applications; Packaging; Silicon; Thermal stability; Wafer scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronics Systemintegration Technology Conference, 2006. 1st
Conference_Location :
Dresden
Print_ISBN :
1-4244-0552-1
Electronic_ISBN :
1-4244-0553-x
Type :
conf
DOI :
10.1109/ESTC.2006.280152
Filename :
4060877
Link To Document :
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