• DocumentCode
    3223519
  • Title

    Manufacturability improvements of inductively coupled plasma etch chambers in PVD tools

  • Author

    Berti, Antonio C. ; Bonner, Edward A.

  • Author_Institution
    Digital Equipment Corp., Hudson, MA, USA
  • fYear
    1995
  • fDate
    13-15 Nov 1995
  • Firstpage
    8
  • Lastpage
    12
  • Abstract
    To accommodate the decreasing gate oxide thickness associated with Digital´s new 0.5 μm technology, the hardware for the pre-metallization sputter etches was retrofitted to reduce plasma damage. This change consisted of replacing the triode sputtering chambers in five sputtering tools with inductively coupled plasma sources. The new hardware not only had to be fully characterized and optimized, but required another climb up the manufacturability learning curve for particulate control and maintainability. Over a year and a half period, new procedures to improve availability were implemented resulting in a 9,000 wafer increase in the number of wafers run between etch chambers preventative maintenance intervals.
  • Keywords
    CMOS integrated circuits; VLSI; integrated circuit yield; sputter etching; 0.5 micron; CMOS; PVD tools; gate oxide thickness; inductively coupled plasma etch chambers; particulate control; pre-metallization sputter etches; preventative maintenance intervals; sputtering tools; wafer run; Atherosclerosis; CMOS process; Hardware; Manufacturing; Plasma applications; Plasma materials processing; Plasma sources; Sputter etching; Sputtering; Testing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Advanced Semiconductor Manufacturing Conference and Workshop, 1995. ASMC 95 Proceedings. IEEE/SEMI 1995
  • ISSN
    1078-8743
  • Print_ISBN
    0-7803-2713-6
  • Type

    conf

  • DOI
    10.1109/ASMC.1995.484328
  • Filename
    484328