A 16-bit 312.5-kHz bandwidth fourth-order one-bit switched-capacitor sigma-delta modulator

Author

Li, Hongyi ; Wang, Yuan ; Jia, Song ; Zhang, Xing

Author_Institution

Key Lab. of Microelectron. Devices & Circuits, Peking Univ., Beijing, China

fYear

2009

fDate

25-27 Dec. 2009

Firstpage

170

Lastpage

173

Abstract

In this paper, a high-resolution medium-frequency single-loop fourth-order 1-bit sigma-delta modulator is implemented in 0.18 Â¿m CMOS technology. The modulator has been presented with an oversampling ratio of 50, clock frequency of 31.25 MHz, 312.5 kHz bandwidth, and achieves a peak SNR of 101.7 dB, which is 16.6-bit resolution, 103 dB dynamic range. The whole circuits consume 58.55-mW from a single 1.8 V supply voltage. The experimental results show a figure-of-merit (FOM) of 170.27 dB. A system to circuit level design is finished in this paper.

Keywords

CMOS integrated circuits; integrated circuit design; modulators; sigma-delta modulation; CMOS technology; bandwidth 312.5 kHz; circuit level design; fourth-order one-bit switched-capacitor sigma-delta modulator; frequency 31.25 MHz; power 58.55 mW; voltage 1.8 V; word length 16 bit; Bandwidth; CMOS technology; Circuit topology; Clocks; Delta modulation; Delta-sigma modulation; Dynamic range; Microelectronics; Signal resolution; Switches; Data conversion; delta-sigma modulator; high resolution; medium frequency.; switch capacitor (SC) integrator;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices and Solid-State Circuits, 2009. EDSSC 2009. IEEE International Conference of

Conference_Location

Xi´an

Print_ISBN

978-1-4244-4297-3

Electronic_ISBN

978-1-4244-4298-0

Type

conf

DOI

10.1109/EDSSC.2009.5394162

Filename

5394162