A CMOS bootstrapped switch with novel clock feed-through compensation

Author

Wu, Xiaofeng ; Liu, Hongxia ; Wu, Yi

Author_Institution

Sch. of Microelectron., Xidian Univ., Xi´´an, China

fYear

2009

fDate

25-27 Dec. 2009

Firstpage

166

Lastpage

169

Abstract

A new clock feed-through compensation configuration and corresponding bootstrapped switch are presented and designed optimally with UMC Mixed-Mode/RF 0.18 Â¿m 1P6M P-Sub Twin-Well CMOS process by orientating and elaborate designing the switch MOSFETs that have influence on the delay path match of the clock boosting circuit. HSPICE simulation results show that the proposed clock feed-through compensation configuration can not only enhance the sampling accuracy under the variations of process, power supply voltage, temperature and capacitors but also decrease even harmonic, high-order odd harmonic and THD on the whole effectively.

Keywords

CMOS integrated circuits; SPICE; bootstrap circuits; clocks; integrated circuit design; switches; CMOS bootstrapped switch; HSPICE simulation; THD; UMC Mixed-Mode; clock feed-through compensation; delay path match; high-order odd harmonic; Boosting; CMOS process; Circuit simulation; Clocks; Delay; MOSFETs; Power system harmonics; Radio frequency; Switches; Switching circuits; bootstrapped switch; clock feed-through compensation; track-and-hold circuit;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices and Solid-State Circuits, 2009. EDSSC 2009. IEEE International Conference of

Conference_Location

Xi´an

Print_ISBN

978-1-4244-4297-3

Electronic_ISBN

978-1-4244-4298-0

Type

conf

DOI

10.1109/EDSSC.2009.5394165

Filename

5394165