Title :
Fault simulation in sequential multi-valued logic networks
Author :
Drechsler, Rolf ; Keim, Martin ; Becker, Bernd
Author_Institution :
Inst. of Comput. Sci., Albert-Ludwigs-Univ., Freiburg, Germany
Abstract :
In this paper we present a fault simulator for Sequential Multi-Valued Logic Networks (SMVLN). With this tool we investigate their random pattern testability (RPT). We discuss a unified approach for fault models in SMVLNs and show that it is possible to describe all static fault models with a global formalism. A large set of experimental results is given that demonstrates the efficiency of our approach. For the first time fault coverages for the Stuck-At Fault Model (SAFM) and Skew Fault Model (SKFM) for large sequential circuits are reported
Keywords :
logic testing; multivalued logic circuits; sequential circuits; fault models; fault simulator; multi-valued logic networks; random pattern testability; sequential circuits; sequential multi-valued logic networks; Circuit faults; Circuit simulation; Circuit synthesis; Circuit testing; Computational modeling; Computer science; Intelligent networks; Logic testing; Manufacturing processes; Multivalued logic;
Conference_Titel :
Multiple-Valued Logic, 1997. Proceedings., 1997 27th International Symposium on
Conference_Location :
Antigonish, NS
Print_ISBN :
0-8186-7910-7
DOI :
10.1109/ISMVL.1997.601389