An 8-b 600MSmaples/s folding and interpolating ADC

Author

Yu, Yunhua ; Ni, Weining ; Zhu, Xubing ; Shi, Haitao ; Qi, Na

Author_Institution

Sch. of Inf. & Control Eng., China Univ. of Pet., Dongying, China

fYear

2009

fDate

25-27 Dec. 2009

Firstpage

79

Lastpage

82

Abstract

This paper presents an 8-bit low power cascaded folding and interpolating analog-to-digital converter (ADC) with Current Mode Logic (CML). A reduction in the number of comparators, equal to the number of times the signal is folded, is obtained. To ensure high speed and low noise, the CML is used. The circuit is implemented in a 0.18-Â¿m CMOS technology, and measures 1.5 mm Ã— 1.5 mm (including pads). The simulation results illustrate a conversion rate of 600 MSamples/s and a power dissipation of less than 150 mW.

Keywords

CMOS logic circuits; analogue-digital conversion; comparators (circuits); current-mode logic; low-power electronics; CMOS technology; comparators; conversion rate; current mode logic; low power cascaded folding analog-to-digital converter; low power interpolating analog-to-digital converter; power dissipation; size 0.18 mum; Analog integrated circuits; Calibration; Equations; Frequency domain analysis; Fuses; MOSFETs; Manufacturing processes; Signal resolution; Solid state circuits; Testing; Analog-to-Digital converter; Current Mode Logic; cascading; folding-and-interpolating;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices and Solid-State Circuits, 2009. EDSSC 2009. IEEE International Conference of

Conference_Location

Xi´an

Print_ISBN

978-1-4244-4297-3

Electronic_ISBN

978-1-4244-4298-0

Type

conf

DOI

10.1109/EDSSC.2009.5394184

Filename

5394184