DocumentCode
3224004
Title
Evaluating workcell layouts
Author
Nehme, David ; McKiddie, Rick
Author_Institution
Pavilion Technol., Austin, TX, USA
fYear
1995
fDate
13-15 Nov 1995
Firstpage
111
Lastpage
114
Abstract
Traditionally, the tools of a wafer fab are laid out into "farms" where tools that perform similar functions are located in one area. With a given process flow and farm layout, estimating material-movement metrics like number of interbay moves and total wafer travel distance is relatively straightforward. This is because there is a one-to-one correspondence between type of processing (etch, photo, etc.) and a given "farm" area. However, in a workcell or mixed farm-workcell layout, there is no such correspondence because similar tools are often located in different areas of the fab. In addition, these distributed tools often support multiple processing steps. Thus, it is a challenge for analysts to evaluate material movement metrics with workcell layouts because of the difficulty in assigning processing steps to particular tools. We present a simple linear programming model that, given the process flows, the start rates, and a fab layout, quickly performs this assignment. The model assigns steps to individual tools or to specific bays with the objective of minimizing wafer travel subject to tool capacity constraints. In performing this analysis, the modeling logic takes into account the fact that a lot of wafers will leave the same tool that it entered. This creates dependencies among assignments of process steps to tools. Linear programming is well suited to handle these types of dependencies. The model is intended for quick evaluations of layouts or given an existing layout, for assigning a processing flow to actual tools. In this paper we give an intuitive explanation of the model, and describe how we used it to evaluate the effect of different workcell designs on material movement.
Keywords
computer aided facilities layout; linear programming; semiconductor device manufacture; farms; linear programming model; material-movement metrics; multiple processing; process flow; semiconductor wafer fabs; tools; workcell layouts; Costs; Etching; Linear programming; Logic programming; Manufacturing processes; Performance analysis; Production facilities; Semiconductor device modeling; Thin films; Yield estimation;
fLanguage
English
Publisher
ieee
Conference_Titel
Advanced Semiconductor Manufacturing Conference and Workshop, 1995. ASMC 95 Proceedings. IEEE/SEMI 1995
ISSN
1078-8743
Print_ISBN
0-7803-2713-6
Type
conf
DOI
10.1109/ASMC.1995.484351
Filename
484351
Link To Document