Design technique for SMDAC without aperture error for 14-b 100MS/s pipelined ADC applications

Author

Xiong, Zhaoxin ; Min Cai

Author_Institution

Sch. of Electron. & Inf. Eng., South China Univ. of Technol., Guangzhou, China

fYear

2009

fDate

25-27 Dec. 2009

Firstpage

83

Lastpage

86

Abstract

This paper presents a new design technique for the first stage of pipeline ADC with the front-end sample-and-hold amplifier (SHA) merged in it is presented. In this technique, the subflash ADC in the first stage of pipelined ADC utilizes the output of the multiplying digital-to-analog converter (MDAC) to make the bit decision, without introducing the aperture error in the first stage of the pipeline ADC. Since the subflash ADC requires just one capacitor to sample the input analog signal and threshold voltage in different clock phases, an area saving as well as high speed is acquired.

Keywords

analogue-digital conversion; digital-analogue conversion; multiplying circuits; sample and hold circuits; SMDAC; multiplying digital-to-analog converter; pipelined ADC application; sample-and-hold amplifier; subflash ADC; Analog-digital conversion; Apertures; Clocks; Digital-analog conversion; Energy consumption; Pipelines; Preamplifiers; Sampling methods; Switches; Voltage; aperture error; capacitor-sharing; low power; multiplying digital-to-analog converter (MDAC); pipelined analog-to-digital converter (ADC);

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices and Solid-State Circuits, 2009. EDSSC 2009. IEEE International Conference of

Conference_Location

Xi´an

Print_ISBN

978-1-4244-4297-3

Electronic_ISBN

978-1-4244-4298-0

Type

conf

DOI

10.1109/EDSSC.2009.5394185

Filename

5394185