Performance analysis of dual-material gate SOI MOSFET

Author

Liu, Hongxia ; Kuang, Qianwei ; Luan, Suzhen ; Hao, Yue

Author_Institution

Sch. of Microelectron., Xidian Univ., Xi´´an, China

fYear

2009

fDate

25-27 Dec. 2009

Firstpage

63

Lastpage

66

Abstract

In this paper, a novel device structure called dual-material gate SOI MOSFET (DMG SOI MOSFET) is proposed to restrain drain-induced barrier lowering (DIBL) and short-channel effect (SCE) for the advanced nanometer process. The analytical threshold voltage model of novel structure device is presented, and the electrical characteristics are analyzed. The DMG SOI MOSFET with high k dielectric shows better performance in suppressing DIBL and enhancing carrier transport efficiency than the conventional SOI MOSFET. The DIBL is reduced with increasing dielectric constant. The analytical threshold voltage model is in good agreement with the two-dimensional device simulator ISE.

Keywords

MOSFET; high-k dielectric thin films; silicon-on-insulator; drain-induced barrier lowering; dual-material gate SOI MOSFET; electrical characteristics; high k dielectric; short-channel effect; Analytical models; CMOS technology; Dielectric materials; Electric variables; High K dielectric materials; High-K gate dielectrics; Leakage current; MOSFET circuits; Performance analysis; Threshold voltage; SOI MOSFET; drain-induced barrier lowering (DIBL); dual material gates (DMG); high k dielectric; short-channel effect (SCE);

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices and Solid-State Circuits, 2009. EDSSC 2009. IEEE International Conference of

Conference_Location

Xi´an

Print_ISBN

978-1-4244-4297-3

Electronic_ISBN

978-1-4244-4298-0

Type

conf

DOI

10.1109/EDSSC.2009.5394188

Filename

5394188