Optimization of sub-100nm transistor gate sidewall spacer process for high-performance applications

As the technology node advances to the next generation, one of the biggest challenges is to achieve minimum pitch while maintaining device performance. This paper describes the details of a novel manufacturing process integration of complementary metal oxide semiconductor (CMOS) transistor architecture, which is incorporated into a sub-micron logic technology on 300 mm wafers. As the gate length is scaling down, the spacer design for CMOS transistor becomes increasingly critical manufacturing process. Moreover, the material of the sidewall spacer itself plays an important role, and its impact on device performance has been intensively discussed. Fabrication process results show that the offset spacer configuration and width can effectively increase the on-state driving current and reduce the off-state leakage current off due to the high vertical fringing electric field effect arising from the side capacitor comprising of gate spacer extension structure. A novel semiconductor fabrication process on gate spacer technology and electrical performance of nano-meter gate structure was included.