DocumentCode
3224245
Title
Design optimization in write speed of multi-level cell application for phase change memory
Author
Lin, Jun-Tin ; Liao, Yi-Bo ; Chiang, Meng-Hsueh ; Chiu, I-Hsuan ; Lin, Chia-Long ; Hsu, Wei-Chou ; Chiang, Pei-Chia ; Sheu, Shyh-Shyuan ; Hsu, Yen-Ya ; Liu, Wen-Hsing ; Su, Keng-Li ; Kao, Ming-Jer ; Tsai, Ming-Jinn
Author_Institution
Dept. of Electron. Eng., Nat. Ilan Univ., Ilan, Taiwan
fYear
2009
fDate
25-27 Dec. 2009
Firstpage
525
Lastpage
528
Abstract
Design optimization to improve write speed of phase change memory is shown achievable by using a physical yet analytical compact PCM model. Our simulation results suggested that the write speed of continuous pulse programming scheme can be optimized and is superior to slow quenching scheme for multi-level cell application.
Keywords
phase change memories; continuous pulse programming scheme; multilevel cell application; phase change memory; quenching scheme; write speed; Amorphous materials; Analytical models; Crystallization; Design optimization; Electrical resistance measurement; Logic; Nonvolatile memory; Phase change materials; Phase change memory; Temperature; MLC; PCM; Phase change memory;
fLanguage
English
Publisher
ieee
Conference_Titel
Electron Devices and Solid-State Circuits, 2009. EDSSC 2009. IEEE International Conference of
Conference_Location
Xi´an
Print_ISBN
978-1-4244-4297-3
Electronic_ISBN
978-1-4244-4298-0
Type
conf
DOI
10.1109/EDSSC.2009.5394196
Filename
5394196
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