Stress effects on self-aligned silicon nanowires junctionless field effect transistors

The heavily doped n-type silicon nanowires (SiNWs) junctionless field effect transistors (JLFETs) are fabricated using the self-aligned process to control the position and direction of SiNWs. Aligned SiNWs are grown across the pre-patterned source and drain under the assistance of the externally applied electric field, which facilitate the subsequent device fabrication. The JLFET exhibits an electron mobility ~ 90 cm²/Vsec, on/off ratio ~ 10⁷, and subthreshold slope ~ 100 mV/dec. Furthermore, the current variation under stress is investigated. It is shown that stress-induced current change reaches maximum when the JLFET is operated in pinch-off condition. Finally, improvement of off current by 98% and subthreshold swing by 15% using compressive stress of 100MPa in the n-type JLFET is achieved.