• DocumentCode
    3224392
  • Title

    BatchQueue: Fast and Memory-Thrifty Core to Core Communication

  • Author

    Homme, Thomas Preud ; Sopena, Julien ; Thomas, Gaël ; Folliot, Bertil

  • Author_Institution
    LIP6, UPMC, Paris, France
  • fYear
    2010
  • fDate
    27-30 Oct. 2010
  • Firstpage
    215
  • Lastpage
    222
  • Abstract
    Sequential applications can take advantage of multi-core systems by way of pipeline parallelism to improve their performance. In such parallelism, core to core communication overhead is the main limit of speedup. This paper presents BatchQueue, a fast and memory-thrifty core to core communication system based on batch processing of whole cache line. BatchQueue is able to send a 32bit word of data in just 12.5 ns on a Xeon X5472 and only needs 2 full cache lines plus 3 byte-sized variables - each on a different cache line for optimal performance - to work. The characteristics of BatchQueue - high throughput and increased latency resulting from its batch processing - makes it well suited for highly communicative tasks with no real time requirements such as monitoring.
  • Keywords
    batch processing (computers); multiprocessing systems; multiprocessor interconnection networks; pipeline processing; BatchQueue; batch processing; cache line; core communication; memory thrifty core; pipeline parallelism; Hardware; Indexes; Monitoring; Multicore processing; Parallel processing; Pipelines; Synchronization;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computer Architecture and High Performance Computing (SBAC-PAD), 2010 22nd International Symposium on
  • Conference_Location
    Petropolis
  • ISSN
    1550-6533
  • Print_ISBN
    978-1-4244-8287-0
  • Electronic_ISBN
    1550-6533
  • Type

    conf

  • DOI
    10.1109/SBAC-PAD.2010.34
  • Filename
    5644946