Title :
Low power and metallic CNT tolerant CNTFET SRAM design
Author :
Zhang, Zhe ; Delgado-Frias, José G.
Author_Institution :
Sch. of Electr. Eng. & Comput. Sci., Washington State Univ., Pullman, WA, USA
Abstract :
A study of an eight-transistor (8-T) SRAM cell and its implementation in carbon nanotube FET (CNTFET) technology is presented. CNTFETs have shown great potential as post-silicon CMOS technology due to their superior transport properties, improved current density and excellent robustness to process, voltage and temperature variations. HSPICE simulations demonstrate great advantages for this cell design over the traditional 6-T structure in terms of static power, dynamic power and noise margin. In current synthesis processes metallic CNTs are grown along with semiconductor CNTs, a metallic tolerant scheme is used to overcome the presence of metallic CNT. The reliability of a large-sized memory is also improved by having memory modules with spare columns.
Keywords :
CMOS memory circuits; SPICE; SRAM chips; carbon nanotube field effect transistors; low-power electronics; CMOS technology; HSPICE simulations; carbon nanotube FET; low power CNTFET SRAM design; metallic CNT tolerant CNTFET SRAM design; CMOS integrated circuits; CNTFETs; Carbon nanotubes; Delay; Inverters; Random access memory; 8-T SRAM cell; Carbon Nanotube FET; leakage current; metallic CNT tolerance;
Conference_Titel :
Nanotechnology (IEEE-NANO), 2011 11th IEEE Conference on
Conference_Location :
Portland, OR
Print_ISBN :
978-1-4577-1514-3
Electronic_ISBN :
1944-9399
DOI :
10.1109/NANO.2011.6144323
