Title :
Low power SET-based SRAM cell design using negative differential conductance
Author :
Syed, Naila ; Chen, Chunhong
Author_Institution :
Dept. of Electr. & Comput. Eng., Univ. of Windsor, Windsor, ON, Canada
Abstract :
This paper presents different performance metrics for single electron tunneling (SET) based static memory cell design using unique negative differential conductance (NDC), with emphasis on power optimization. The read/write operations for the memory cell are briefly discussed. All simulations are conducted using the Monte Carlo method from SIMON tools.
Keywords :
Monte Carlo methods; SRAM chips; circuit optimisation; low-power electronics; single electron transistors; Monte Carlo method; NDC; SET based static memory cell design; SIMON tools; low power SET-based SRAM cell design; negative differential conductance; performance metrics; power optimization; read/write operations; single electron tunneling based static memory cell design; Capacitance; Computer architecture; Logic gates; Microprocessors; Random access memory; Reliability; Switches; SRAM cell; Single electron devices; low power; negative differential conductance;
Conference_Titel :
Nanotechnology (IEEE-NANO), 2011 11th IEEE Conference on
Conference_Location :
Portland, OR
Print_ISBN :
978-1-4577-1514-3
Electronic_ISBN :
1944-9399
DOI :
10.1109/NANO.2011.6144340
