DocumentCode
322491
Title
Reducing overheads in distributed shared memory systems
Author
Morris, J. ; Gregg, R.R. ; Herbert, D. ; McCoull, J.
Author_Institution
Dept. of Electr. & Electron. Eng., Western Australia Univ., Nedlands, WA, Australia
Volume
1
fYear
1997
fDate
7-10 Jan 1997
Firstpage
244
Abstract
Shared memory machines have two major overheads: keeping caches coherent and managing the multiple threads of computation which enable tolerance of very long memory latencies. Thetis is a hybrid architecture providing both shared memory and efficient message passing; it will be built from `commodity´ components and consists of sites with a small number of computation processors and a separate, programmable, auxiliary processor. The auxiliary processor performs overhead tasks, e.g. maintenance of cache directories, management of memory and thread queues; placed on its own bus, it does not block or delay memory accesses from computation processors which are not waiting for it. We describe how the use of a threaded variant of C (which has a functional style) enables the run-time system to dynamically determine coherence needs-dramatically reducing the overhead of maintaining coherent caches in a shared memory machine
Keywords
cache storage; message passing; shared memory systems; Thetis; auxiliary processor; cache directories; coherent caches; computation processors; distributed shared memory systems; hybrid architecture; long memory latencies; message passing; multiple threads; overheads; run-time system; shared memory machine; Access protocols; Coherence; Computer architecture; Computer science; Costs; Delay; Field programmable gate arrays; Hardware; Memory management; Message passing; Parallel programming; Yarn;
fLanguage
English
Publisher
ieee
Conference_Titel
System Sciences, 1997, Proceedings of the Thirtieth Hawaii International Conference on
Conference_Location
Wailea, HI
ISSN
1060-3425
Print_ISBN
0-8186-7743-0
Type
conf
DOI
10.1109/HICSS.1997.667263
Filename
667263
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