Title :
ESD protection consideration in nanoscale CMOS technology
Author :
Ker, Ming-Dou ; Lin, Chun-Yu
Author_Institution :
Inst. of Electron., Nat. Chiao-Tung Univ., Hsinchu, Taiwan
Abstract :
The thinner gate oxide in nanoscale CMOS technologies seriously degraded the electrostatic discharge (ESD) robustness of IC products. As the feature sizes in nanoscale CMOS technologies are further scaling down, the on-chip ESD protection designs are more challenging. The ESD protection considerations, including ESD design window, area efficiency, leakage current, and high-voltage tolerance, were presented in this abstract. Some possible solutions against these issues in nanoscale CMOS technologies were also included in this paper.
Keywords :
CMOS integrated circuits; electrostatic discharge; leakage currents; ESD design window; IC product; area efficiency; electrostatic discharge; high-voltage tolerance; leakage current; nanoscale CMOS technology; on-chip ESD protection design; thinner gate oxide; CMOS integrated circuits; CMOS technology; Clamps; Electrostatic discharges; Leakage current; Logic gates; Nanoscale devices; CMOS; electrostatic discharge (ESD); on-chip ESD protection;
Conference_Titel :
Nanotechnology (IEEE-NANO), 2011 11th IEEE Conference on
Conference_Location :
Portland, OR
Print_ISBN :
978-1-4577-1514-3
Electronic_ISBN :
1944-9399
DOI :
10.1109/NANO.2011.6144345
