Title :
Design and implementation of ΣΔ AD converter
Author :
Huang, Jie ; Cui, Yingying ; Cui, Xiaoxin ; Yu, Dunshan
Author_Institution :
Inst. of Microelectron., Peking Univ., Beijing, China
Abstract :
An efficient design and implementation of a sigma-delta (ΣΔ) analog-to-digital (AD) converter which realizes 16 bit resolution is described in this paper. In 16 and 32 times decimation lowpass mode, and 32 times decimation bandpass mode, signal-to-noise ratio (SNR) achieves 90 dB respectively. The ΣΔ modulator is designed in 2-1-1-1 multistage noise shaping (MASH) structure. The decimation filter which is designed in multistage cascade structure is realized with add-and-shift scheme to avoid the usage of any multiplier. The AD converter is implemented in a 0.35μm technology, the area of the ΣΔ modulator is 4.1mm??1.9 mm, the core area of the decimation filter is 5.4mm??3.6mm1.
Keywords :
analogue-digital conversion; decimation filter; multistage noise shaping structure; sigma-delta analog-to-digital converter; signal-to-noise ratio; size 0.35 μm; MASH; decimation; noise shaping; oversampling;
Conference_Titel :
Electron Devices and Solid-State Circuits, 2009. EDSSC 2009. IEEE International Conference of
Conference_Location :
Xi´an
Print_ISBN :
978-1-4244-4297-3
Electronic_ISBN :
978-1-4244-4298-0
DOI :
10.1109/EDSSC.2009.5394247
