Design of a novel 8-bit 0.35-µm BiCMOS pipelined ADC

Author

Xi, Gaijuan ; Liu, Hongxia ; Yu, XiangHong

Author_Institution

Sch. of Microelectron., Xidian Univ., Xi´´an, China

fYear

2009

fDate

25-27 Dec. 2009

Firstpage

342

Lastpage

345

Abstract

The pipelined ADC can keep high speed and low power consumption when it achieves high conversion accuracy, it can compromise between speed, conversion accuracy, power consumption and chip area. It is very suitable to be used in system integration and portable devices. This paper presents a novel pipelined analog-to-digital converter (ADC). Based on 0.35 μm BiCMOS process, the design is verified using the sample frequency of 250 MHz. The results show that signal to noise ratio (SNR) and Spurious Free dynamic range (SFDR) can reach 46-dB and 64.8-dB respectively. The power consumption of the key A/D circuit is 118 mW when the supply voltage is 3.3 V.

Keywords

BiCMOS integrated circuits; analogue-digital conversion; integrated circuit design; low-power electronics; pipeline arithmetic; BiCMOS pipelined ADC; BiCMOS process; conversion accuracy; frequency 250 MHz; low power consumption; pipelined analog-to-digital converter; portable devices; power 118 mW; signal to noise ratio; size 35 μm; spurious free dynamic range; system integration; voltage 3.3 V; BiCMOS; analog-to-digital converter (ADC); latched-comparator; sampling and holding circuit;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices and Solid-State Circuits, 2009. EDSSC 2009. IEEE International Conference of

Conference_Location

Xi´an

Print_ISBN

978-1-4244-4297-3

Electronic_ISBN

978-1-4244-4298-0

Type

conf

DOI

10.1109/EDSSC.2009.5394248

Filename

5394248