Title :
An optimized design for a decimation filter and implementation for Sigma-Delta ADC
Author :
Cui, Yingying ; Huang, Jie ; Wu, Lingjuan ; Cui, Xiaoxin ; Yu, Dunshan
Author_Institution :
Inst. of Microelectron., Peking Univ., Beijing, China
Abstract :
The area, speed, and power consumption of over-sampled data converters are governed largely by the decimation filters in Sigma-Delta Analog/Digital converters(ADC) and multiplication is the core operation of the digital filter, so the performance of digital system is determined by multiplication. This paper compares four different popular methods: Conventional multiplications and additions; full custom distributed arithmetic (DA) scheme; Add-and-Shift method with CSD encoding; advanced sub-expression sharing algorithm. Each scheme is analyzed in detail including implementing process and the experimental results are given to evaluate each scheme. All of these implementations are aimed to implement using Design Compiler. Then this paper presents an optimized circuit for the decimation filter and the decimation filter for Sigma-Delta ADC is implemented using 0.35 ¿m CMOS technology, with an approximate silicon area of 19 mm.
Keywords :
CMOS integrated circuits; FIR filters; arithmetic codes; circuit layout CAD; circuit optimisation; distributed arithmetic; sigma-delta modulation; Add-and-Shift method; CSD encoding; advanced sub-expression sharing algorithm; data converters; decimation filter; design compiler; distributed arithmetic scheme; optimized circuit; sigma-delta ADC; Analog-digital conversion; Arithmetic; CMOS technology; Circuits; Delta-sigma modulation; Design optimization; Digital filters; Digital systems; Encoding; Energy consumption; CSD encoding; decimation filter; distributed arithmetic; sigma-delta ADC;
Conference_Titel :
Electron Devices and Solid-State Circuits, 2009. EDSSC 2009. IEEE International Conference of
Conference_Location :
Xi´an
Print_ISBN :
978-1-4244-4297-3
Electronic_ISBN :
978-1-4244-4298-0
DOI :
10.1109/EDSSC.2009.5394251
