DocumentCode :
3225290
Title :
Design and Implementation of a High-Performance Microprocessor Cache Compression Algorithm
Author :
Chen, Xi ; Yang, Lei ; Lekatsas, Haris ; Dick, Robert P. ; Shang, Li
Author_Institution :
Northwestern Univ., Evanston
fYear :
2008
fDate :
25-27 March 2008
Firstpage :
43
Lastpage :
52
Abstract :
Abstract Researchers have proposed using hardware data compression units within the memory hierarchies of microprocessors in order to improve performance, energy efficiency, and functionality. However, most past work, and in particular work on cache compression, has made unsubstantiated assumptions about the performance, power consumption, and area overheads of the required compression hardware. We present a lossless compression algorithm that has been designed for on-line memory hierarchy compression, and cache compression in particular. We reduced our algorithm to a register transfer level hardware implementation, permitting performance, power consumption, and area estimation. The results of experiments comparing our work to previous work are presented.
Keywords :
cache storage; data compression; microcomputers; cache compression algorithm; hardware data compression; high-performance microprocessor; lossless compression algorithm; on-line memory hierarchy compression; Algorithm design and analysis; Compression algorithms; Costs; Data compression; Delay; Energy consumption; Energy efficiency; Flexible printed circuits; Hardware; Microprocessors;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Data Compression Conference, 2008. DCC 2008
Conference_Location :
Snowbird, UT
ISSN :
1068-0314
Print_ISBN :
978-0-7695-3121-2
Type :
conf
DOI :
10.1109/DCC.2008.90
Filename :
4483282
Link To Document :
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