Title :
Hardware implementation of a VDPCM using parallel processing architecture
Author :
Thyagarajan, K.S.
Author_Institution :
Dept. of Electr. & Comput. Eng., San Diego State Univ., CA, USA
Abstract :
A parallel processing architecture is described to implement the VDPCM encoder/decoder hardware for real-time image coding applications. The architecture consists of processing elements in modular form, and each module is designed around AT&T´s DSP32 chip. The system is flexible and expandable. The hardware was used to encode images at a rate of 0.5 bit pixel, and results are given. The hardware results are in agreement with the computer simulations.<>
Keywords :
codecs; digital signal processing chips; encoding; parallel architectures; picture processing; pulse-code modulation; DSP32 chip; codecs; computer simulations; decoder; encoder; parallel processing architecture; real-time image coding; Computer architecture; Concurrent computing; Costs; Decoding; Electrical capacitance tomography; Hardware; Logic arrays; Parallel processing; Pixel; Speech processing;
Conference_Titel :
Communications, Computers and Signal Processing, 1989. Conference Proceeding., IEEE Pacific Rim Conference on
Conference_Location :
Victoria, BC, Canada
DOI :
10.1109/PACRIM.1989.48446
