DocumentCode
3225384
Title
VLSI implementation of adaptive bit/serial IIR filters
Author
Badyal, Rajeev ; Kiaei, Sayfe
Author_Institution
Hewlett Packard, Corvallis, OR, USA
fYear
1989
fDate
1-2 June 1989
Firstpage
650
Lastpage
652
Abstract
A new structure for the VLSI implementation of a bit/serial adaptive IIR filter is presented. The system is built at a bit level consisting of only gated full adders. This approach allows recursive operation of the IIR filter to be implemented with minimal delay time and chip area. The coefficients of the filter can be updated in real time for the time invariant and adaptive filtering. The fourth-order filter is implemented on a 2- mu m CMOS technology clocked at 50 MHz.<>
Keywords
CMOS integrated circuits; VLSI; adaptive filters; digital filters; 2 micron; 2- mu m CMOS technology; 50 MHz; VHF; VLSI; adaptive bit/serial IIR filters; adaptive filtering; delay time; fourth-order filter; gated full adders; recursive operation; time invariant filtering; CMOS technology; Clocks; Computer architecture; Delay; Finite impulse response filter; IIR filters; Pins; Signal processing algorithms; Throughput; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Communications, Computers and Signal Processing, 1989. Conference Proceeding., IEEE Pacific Rim Conference on
Conference_Location
Victoria, BC, Canada
Type
conf
DOI
10.1109/PACRIM.1989.48447
Filename
48447
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