DocumentCode :
3225681
Title :
An evolvable NoC-based spiking neural network architecture
Author :
Morgan, F. ; Cawley, S. ; Harkin, J. ; McGinley, B. ; McDaid, L. ; Pande, S.
Author_Institution :
Bio-Inspired Electron. & Reconfigurable Comput. Res. Group (BIRC), Nat. Univ. of Ireland, Galway, Ireland
fYear :
2009
fDate :
10-11 June 2009
Firstpage :
1
Lastpage :
6
Abstract :
Nature employs bio-inspired concepts such as evolution and learning to develop complex and intelligent organisms, capable of adaptation and fault tolerance. Brain-inspired paradigms such as Spiking Neural Networks (SNNs) offer the potential of elegant, low-power and robust methods of performing computing. Previous work by the authors reports a reconfigurable mixed signal Network on Chip (NoC)-based SNN architecture, with reconfigurable analogue neuron cell and digital NoC The SNN architecture includes an array of neural tiles, each incorporating a NoC router for packet-based neuron interconnect. This paper presents a Genetic Algorithm (GA) based evolution framework which interacts with the SNN architecture to evolve SNN-based solutions to problems. Simulation results are presented which verify the adaptability of the reconfigurable NoC-based SNN architecture in evolving a solution for the XOR benchmark problem. Results on the synthesised neural tile area utilisation for FPGAs are also presented. This work contributes to the realisation of a large scale reconfigurable mixed signal hardware platform for SNNs.
Keywords :
fault tolerant computing; field programmable gate arrays; genetic algorithms; network-on-chip; neural net architecture; reconfigurable architectures; FPGAs; Network on Chip based SNN architecture; NoC router; XOR benchmark problem; analogue neuron cell; brain inspired paradigms; digital NoC; evolvable NoC based spiking neural network architecture; fault tolerance; genetic algorithm based evolution framework; large scale reconfigurable mixed signal hardware platform; neural tiles; packet based neuron interconnect; Genetic Algorithm; Network on Chip; Reconfigurable Spiking Neural Networks;
fLanguage :
English
Publisher :
iet
Conference_Titel :
Signals and Systems Conference (ISSC 2009), IET Irish
Conference_Location :
Dublin
Type :
conf
DOI :
10.1049/cp.2009.1732
Filename :
5524665
Link To Document :
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