Jitter model of Fraction-N Synthesizer influenced by ΣΔ quantization noise

Author

Tao, Huibin ; Guo, Yixin ; Shao, Zhibiao

Author_Institution

Sch. of Electron. & Inf., Xi´´an Jiaotong Univ., Xi´´an, China

fYear

2009

fDate

25-27 Dec. 2009

Firstpage

262

Lastpage

265

Abstract

Sigma-Delta Modulation is an essential factor for high performance Fraction-N Synthesizer and the jitter of the output signal is one of the most important parameter to characterize the performance of synthesizer. In this paper, we presents a calculation model for jitter, which includes the phase noise model of Fraction-N divider with Sigma-Delta Modulation noise transfer model of the loop and the model of getting jitter from the output phase noise VCO. With this model, we can easily get all kinds of jitter of the loop output signal exactly. So it provides important theoretic foundation for the design of fraction-N synthesize.

Keywords

frequency synthesizers; jitter; phase locked loops; phase modulation; phase noise; quantisation (signal); sigma-delta modulation; voltage-controlled oscillators; VCO; clock jitter; fraction-N divider; fraction-N synthesizer; jitter model; loop output signal; output phase noise; output signal jitter; phase noise model; sigma-delta modulation noise transfer model; sigma-delta quantization noise; voltage controlled oscillator; Fraction-N; Jitter; Sigma-Delta Modulation;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices and Solid-State Circuits, 2009. EDSSC 2009. IEEE International Conference of

Conference_Location

Xi´an

Print_ISBN

978-1-4244-4297-3

Electronic_ISBN

978-1-4244-4298-0

Type

conf

DOI

10.1109/EDSSC.2009.5394271

Filename

5394271