FPGA implementation of new real-time image encryption based switching chaotic systems

Chaos-based encryption has suggested a new and efficient way to deal with the problem of fast and highly secure image encryption. In this paper, a new chaotic key generator for image encryption and its FPGA implementation based on a chaos switching rule between Lorenz´s and Lm´s non-linear systems is proposed for designing a real-time secure symmetric encryption scheme. The originality of this new scheme is that it allows a low cost image encryption for embedded systems while still providing a good trade-off between performance and hardware resources. Our experimental results have demonstrated the feasibility and the efficiency of our secure solution on Xilinx FPGA virtex technology. Thorough experimental tests are carried out with detailed analysis, demonstrating the high security and fast encryption speed of the new scheme while still able to resist statistical and Key analysis attacks.