New noise-tolerant dynamic circuit design

Dynamic circuit is suitable for high-speed application, but often suffers from noise related reliability problems which become increasingly prominent as the technology are entering into the scores of nano meter era. This paper presented a new dynamic circuit scheme, which could achieve higher noise margin without sacrificing much power consumption and delay time. This design achieves a higher noise margin (1.2 V) by finely tuning the transistor size. The effectiveness of new scheme is demonstrated in both NMOS series and parallel circuits. The simulation result shows that, compared with other published work, the proposed structure has the highest noise margin for the same power-delay product (PDP)¹.